Available Specifications
Currently there are 37 PICMG Specifications available, in 4 groups.
PICMG 1.x Series - Passive Backplane PCI
| PICMG 1.0 R2.0 PCI-ISA Card Edge Connector for Single Board Computer |
Define CPU form factor and back
plane connector for PCI-ISA passive backplanes. |
| PICMG 1.1 R1.02 PCI Bridge Board for Single Board |
Define a form factor and
backplane connector layout for PCI-PCI bridge boards. |
| PICMG 1.2 R1.0 EmbeddedPCI-X Specification (ePCI-X) |
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| PICMG
1.3 R1.0 System Host Board PCI Expess Specification |
This specification enhances the capability of SHBs (System Host Boards) by adding support for PCI Express links, increasing the power available to the SHB, and improving the mechanical reliability of the SHB. |
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PICMG 2.x Series - CompactPCI
| PICMG
2.0 R3.0 Compact PCI Core Specification |
CompactPCI Base specification |
| PICMG
2.1 R2.0 CompactPCI Hot Swap |
Define pin sequencing and other enabling hardware
technologies, and defines the software architecture required, to support
live insertion and extraction of boards in a running CompactPCI system. |
| PICMG
2.2 R1.0 VME64x on CompactPCI |
Define pin assignments for the VME64 Extensions, as
standardized under the auspices of ANSI and VITA, on J5/P4 and J5/P5 of a
CompactPCI backplane. |
| PICMG
2.3 R1.0 PMC I/O Pin Assignments on CompactPCI |
Define user I/O pin mappings from IEEE 1386 PMC sites to
J3/P3, J4/P4, and J5/P5 on a CompactPCI. |
| PICMG
2.4 R1.0 IP I/O Pin Assignments on CompactPCI |
Define user I/O pin mappings from ANSI/VITA standard IP
sites to J3/P3, J4/P4 and J5/P5 on a CompactPCI. |
| PICMG
2.5 R1.0 CompactPCI Computer Telephony |
Define the utilization of CompactPCI user definable pins
for the computer telephony functions of standard TDM bus, telephony rear IO,
48 VDC and ringing distribution in a 6U chassis environment. |
| PICMG
2.7 R1.0 CompactPCI 6U Dual System Slot Specification |
Define a means for CompactPCI CPU boards to drive two
independent PCI bus segments in a 6U environment. The bottom bus connected
to J1/J2 is referred to as PCI Bus A, the top bus connected to J4/J5 is
referred to as PCI Bus B. For the purposes of this specification, the
relationship between Bus A and Bus B is not specified. |
| PICMG
2.9 R1.0 CompactPCI System Management Specification |
Defines a secondary bus which allows the host or other
subordinate processors to interrogate and control CompactPCI cards. Serial
number, revision level, and operating temperature are examples of
information the cards could make available. In fault tolerant applications,
for example, a host could send commands over the system management bus to
reset or cut power to failed cards. |
| PICMG 2.10 R1.0 CompactPCI Keying of CompactPCI Board and Backplanes |
Created to deal with overlapping uses of CompactPCI's user-definable pins, where use of the keying mechanisms defined in IEC 61076-4-101 for the J4/P4 connector and in IEEE 1101.10 for handle and card guide hardware will be required. It provides a single reference document and reduces the risk of duplicated use. |
| PICMG
2.11 R1.0 CompactPCI Power Interface |
Defines the electrical and mechanical requirements relating
to the functionality and interoperability of 3U and 6U form factor plug-in
power modules in CompactPCI systems. |
| PICMG
2.12 R2.0 CompactPCI Hot Swap Infrastructure Interface |
Define standard platform interfaces for supporting
CompactPCI Hot Swap operating systems for full and High Availability (HA)
I/O hot swap system models. This includes access to hot swap boards that
incorporate alternate implementations of the Hot Swap Control and Status
Register (HS_CSR). |
| PICMG
2.14 R1.0 CompactPCI Multi Computing Specification |
Defines packet-based communications between heterogeneous PCI agents (multi-computing) within the CompactPCI system architecture. |
| PICMG 2.15 R1.0 CompactPCI PCI Telecom Mezzanine/Carrier Card (PTMC) |
The PCI Telecom Mezzanine Card Specification defines pin locations on Pn3/Jn3 and Pn4/Jn4 for signals of the RMII, Ethernet PHY Management Interface, UTOPIA Level 1, UTOPIA Level 2, POS-PHY Level 2, and ECTF H.110 interfaces. Restrictions and relaxations of implementation requirements for these specifications are provided. PTMC is based on the four connector standards PCI Mezzanine Card (PMC). The PTMC provides all of the traditional PMC 32-bit PCI signals on the Pn1 and Pn2 connectors, yet it also supports specialized telecom interfaces on Pn3 and Pn4. PTMC leverages the success, form factor, and functionality of the of PMC series peripheral mezzanine cards, but is not a replacement for PMC. It will coexist with PMC and support three popular industry standard telecom bus interfaces and Ethernet. |
| PICMG
2.16 R1.0 CompactPCI Packet Switching Backplane |
To rapidly develop a CompactPCI Packet Switching Backplane
specification that is an extension of the PICMG 2.x family of specifications
by overlaying a packet based switching architecture on top of CompactPCI to
create an Embedded System Area Network (ESAN). The CompactPCI Packet Switching Backplane provides a redundant, switched 10/100/1000 Ethernet network within a Compact PCI chassis providing connectivity between all slots using a star topology. It is intended to coexist with 64 bit CompactPCI and H.110. Special slot(s) for active switching fabric element(s), which may be redundant, are also specified. |
| PICMG
2.17 R1.0 CompactPCI StarFabric specification |
To rapidly develop a PICMG 2.17 StarFabric CompactPCI
specification that defines backplane, node card and switch card requirements
that are compatible with both the StarFabric Protocol Specification and
appropriate existing PICMG Specifications. The StarFabric Interconnect specifications will define redundant, switched, high-speed point-to-point connectivity among some or all slots using StarFabric switch cards. The StarFabric interconnect will coexist with 64 bit PCI, CompactPCI and H.110. Optional compatibility with cPSB (PICMG 2.16) will be specified. Systems, which take advantage of StarFabric features, can be designed to utilize existing single board computers (SBCs) and node cards.Special slot(s) for active switching fabric element(s), which may be redundant, will also be specified. |
| PICMG
2.18 R1.0 CompactPCI Serial RapidIO Specification |
To define backplane, node board, and switch board
requirements that are compatible with both the Serial RapidIO Architecture
Specification and appropriate existing PICMG Specifications. This
specification will provide designers, manufacturers, and integrators with a
common set of requirements for implementing backplanes, boards and chassis
to deliver the benefits of Serial RapidIO interconnect, including high
bandwidth (up to 20Gbps per slot in each direction), scalability,
high-availability features, PCI-compatibility and the ability to carry all
required data on a single packet-switched interconnect. |
| PICMG
2.20 R1.0 CompactPCI Serial Mesh Backplane Specification |
This specification defines a high-speed serial fabric for
CompactPCI platforms. The purpose of this fabric is to enhance the data
transport –capability of CompactPCI platforms for high-end applications
like telecom multi-service routers and gateways while maintaining
compatibility with existing CompactPCI standards to protect invest. |
| PICMG EXP.0 R1.0 CompactPCI Express Specification | This specification's objective is to bring PCI Express technology to the popular PICMG 2.0 CompactPCI form factor. This specification is intended to meet the future market needs of the CompactPCI, PXI, military, and aerospace markets and defines the connector, electrical, and mechanical requirements of 3U/6U System Boards, Peripheral Boards, Switch Boards and Backplanes. |
| PICMG 2.30 R1.0 CompactPCI PlusIO |
This specification adds the serial busses PCI Express, Ethernet, SATA, SAS and USB extensions to the CompactPCI family of specifications while preserving PCI bus connectivity. The specification defines the use of the previously reserved rear I/O pins for the 32-bit CompactPCI system slot with high-speed serial signals. |
| PICMG CPCI-S.0 R1.0 CompactPCI Serial |
This specification defines a modular computer system, consisting of
CompactPCI Serial defines the support of
PCI Express, SATA/SAS, USB and Ethernet, concurrently. PCI Express, SATA/SAS
and USB are arranged as a simple star architecture. Ethernet is a full
mesh. Switch boards are not required and therefore not described. To
support the high-speed serial interfaces a connector is introduced which
is compatible to [IEEE1101]. |
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PICMG 3.x Series - Advanced Telecommunication Computer Architecture, AdvancedTCA, TCA
| PICMG
3.0 R3.0 AdvancedTCA Serial Interconnect |
The PICMG 3.0 specification will establish a cost
effective, fabric based modular, interoperable and scalable architecture for
converging communications and data networking applications. Mechanical,
thermal management, power distribution and system management will be defined
in this “core” specification, but it will be fabric agnostic so as to
support transitions in technology over time or by application. The focus for
features will be telecommunications carrier grade [Reliability,
Availability, Serviceability (RAS)] oriented with a second order objective
to accelerate the adoption in highly available data center applications.
PICMG 3.0 and its subsidiary specifications will provide a solution for
markets that are currently underserved by existing standard and proprietary
approaches. PICMG 3.0 is intended for higher performance applications and is legacy free in terms of the direct electrical support for existing bus-based solutions such as PCI or H.110. The mechanical elements will be based on existing IEC 60297-3-xxx standards (Eurocard equipment practice) with additional requirements specified to meet the intended applications. A robust system management scheme will be defined. Equipment practice for power and cooling at the board and shelf level will be defined. Specific regulatory specifications will be referenced within PICMG 3.0 to give guidance to board, shelf and frame manufacturers building carrier grade equipment. The PICMG 3.0 “core” specification will specify board, backplane and shelf mechanicals, power distribution and the connectivity required for system management. Multiple zones for connectors and their alignment and keying features will also be defined, and the physical mapping to a connector family will be specified. Specific fabric definitions will be undertaken on subsidiary specifications (PICMG 3.1, PICMG 3.2, etc.). In this manner, component interoperability will be defined by the combined PICMG 3.0 core specification and a subsidiary fabric specification. It is the intent to develop the core specification and subsidiary specifications as nearly in parallel as possible. |
| PICMG
3.1 R1.0 AdvancedTCA Ethernet/Fibre Channel |
Develop a fabric specification that will support Ethernet
(IEEE 802.3) and Fibre Channel (INCITS T11) data links (L2) and physical
layers (L1) over the PICMG 3.0 generic backplane interconnect. The intended
implementation practice will normally include at least one link of Ethernet,
and usage of Fibre Channel will be optional. |
| PICMG
3.2 R1.0 AdvancedTCA InfiniBand |
The PICMG 3.2 specification uses InfiniBand physical layers
and protocols in a PICMG 3.0 compliant backplane to interconnect a number of
circuit boards on a shelf. Several different backplane interconnection
topologies are available, including dual star, quad star and full mesh.
InfiniBand signaling rates of 2.5Gb/s (and optionally up to 10Gb/s) are
supported on each link. The PICMG 3.2 specification will define how InfiniBand transport is mapped onto the PICMG 3.0 base. It will specify the link physical layers, protocols, and protocol mappings needed to implement multi-vendor, interoperable systems. Specification of addressing schemes, virtual lane mappings, initialization, keying, hot swap support, and hardware management will be included. PICMG 3.2 will fully comply with, and build upon, the base provided by PICMG 3.0, including mechanical design, power, cooling and hardware management framework. The PICMG 3.2 specification is intended to coexist with and complement the other specifications based on PICMG 3.0, including PICMG 3.1 (using Ethernet backplane links) and PICMG 3.3 (using StarFabric backplane links). |
| PICMG
3.3 R1.0 AdvancedTCA StarFabric |
The PICMG 3.3 specification will define the electrical
environment for StarFabric as a fabric interface for AdvancedTCA system
applications. In addition, the specification will reference the PICMG 3.4
specification for PCI Express™ implementations that could interoperate
with PICMG 3.3 cards. PCI Express and StarFabric capabilities and
implementations are highly aligned and can be interoperable through an
adaptive bridging scheme. StarFabric utilizes a physical layer made up of
pairs of 622Mbps differential signaling. PCI Express utilizes a physical
layer with 4 times the bandwidth made up of pairs (lanes) of 2.5Gbps
differential signaling with future speed upgrades possible. |
| PICMG
3.4 R1.0 AdvancedTCA for PCI Express Architecture |
The PICMG 3.4 specification will define the electrical
environment for PCI Express as a fabric interface for AdvancedTCA™ system
applications. This electrical environment will support PCI Express™ Core
and PCI Express Advanced Switching silicon implementations. The
specification will define switched, high-speed, low latency point-to-point
connectivity among node, fabric (switch hub) and full mesh boards for PCI
Express interconnects. Pin mappings for node and fabric cards/slots will be
defined for the dual star, dual-dual star, and mesh fabric topologies
defined in the PICMG 3.0 core specification. |
| PICMG
3.5 R1.0 Serial RapidIO™ for AdvancedTCA Systems |
This specification defines the design rules and guidelines for implemention of RapidIO-based node and fabric cards based on the PICMG 3.0 standard. |
| PICMG
IRTM.0 AdvancedTCA Intelligent Rear Transition Moldule |
This specification adds system management to rear transition modules used with AdvancedTCA node boards. It also defines an RTM repository to provide details on various RTM implementations supported by the industry. |
Supporting Specifications
| PICMG SFP.0
R1.0 System Fabric Plane Format |
SFP.0 defines the implementation of a System
Fabric Plane Format. The SFP framework is intended to be a standard way for modules to communicate in Comm Fabric type applications, such as routers, wireless radio network controllers, voice over packet gateways, media servers, and firewalls. |
| PICMG SFP.1
R1.0 Internal TDM |
This specifications
specifies the I-TDM protocol. New modular architectures and standards (like PICMG 3.x) define communication systems that do not include a TDM backplane or TDM interconnect technology for LAN attached communication modules. TDM traffic has not been eliminated, just the legacy H.1x0 bus in next generation modular systems. Packet back-planes and LANs have replaced legacy physical interconnects, but there still needs to be a standard way of transporting TDM traffic from one module to another. |
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Other Specifications
| PICMG
AMC.0 R2.0 Advanced Mezzanine Card Base Specification |
The PICMG AMC.0 specification defines the base level
requirements for a wide-range of high-speed mezzanine cards optimized for,
but not limited to, AdvancedTCA® Carriers. This base specification defines
the common elements for each implementation including mechanical,
management, power, thermal, and interconnect. Subsidiary specifications will
define the usage requirements for each interface implementation. Target
interfaces include PCI Express, Advanced Switching, Serial RapidIO and
Gigabit Ethernet. |
| PICMG
AMC.1 R2.0 PCI Express and Advanced Switching on AdvancedMC |
The PICMG AMC.1 specification defines the implementation of
PCI Express and Advanced Switching on AMC.0 Modules and Carriers. it is
dependent upon and leverages AMC.0 for definition of the mezzanine's
mechanical, interconnect, management, power and thermal requirements. |
| PICMG AMC.2 R1.0 Ethernet Advanced Mezzanine Card |
This AMC.0 subsidiary specification adds Ethernet Fabric to Advanced Mezzanine Card. The base specification (AMC.0) defines the Module’s mechanical, interconnect, management, power and thermal requirements. The AMC.2 specification is limited in scope to defining link usage, management and Electronic-Keying (E-Keying) parameters for Gigabit Ethernet (GbE) and 10 Gigabit Ethernet (10 GbE) on AMCs and Carrier Boards |
|
PICMG AMC.3 R1.0
|
AMC.3 layers Serial Attached SCSI (SAS), Serial ATA (SATA) and Fibre Channel interfaces for storage devices on the base AMC.0 specification. |
| PICMG MTCA.0 R1.0 MicroTCA |
MicroTCA, as developed under PICMG, is based on the Advanced Mezzanine Card concept, in which AMC cards plug directly into a backplane, creating physically small but very powerful system in 4U height and 300mm in depth. This not only reduces size, but also cost: target cost for a production of MicroTCA system is around €500, making it suitable for a much wider range of applications. |
| PICMG MTCA.1 R1.0 Air Cooled Rugged MicroTCA |
The Air Cooled Rugged
Micro Telecommunications Computing Architecture (MicroTCA)
specification defines the requirements for a System that meets more
stringent levels and cycles of temperature, shock, vibration, and
humidity than those defined in MicroTCA.0. This specification, which must be used in conjunction with MicroTCA.0, provides the additional requirements necessary for a System with the additional capabilities to meet the more rugged requirements of outside plant telecom, industrial and aerospace environments. In addition it defines the test setups required to test MicroTCA components and Systems. |
| PICMG MTCA.3 R1.0 Hardened Conduction Cooled MicroTCA |
This specification defines the requirements for systems that meet more stringent levels of temperature, shock, vibration, and other environmental conditions. This enables development and deployment of MicroTCA in more rugged environments like outdoor telecom, military, shipboard and other harsh mobile equipment environments. |
| PICMG COM.0 R2.0 COM Express™ Module Specification |
The original Computer-On-Module (COM) specification was adopted by PICMG in 2005, and was designed to reduce time-to-market on specialized platforms used in industrial, medical, military, scientific and telecommunication applications. The COM Express Revision 2.0 specification allows developers to focus on their specialized I/O requirements, without worrying about the complex interactions of CPUs, RAM, Chipsets and other basic elements that occur on the module. This recent revision helps to ensure that COM Express modules are prepared for future computer architectures while accommodating backward compatibly with older modules. Some of the more important changes include:
The revision also includes enhanced security and environmental monitoring support. |
| PICMG HPM.1 Hardware Platform Management IPM Controller Firmware Upgrade Specification | This hardware
platform management specification defines a Firmware Upgrade facility
for PICMG IPM Controllers, as specified in the AdvancedTCA, AdvancedMC
and MicroTCA specifications. References to IPM Controller in this
specification are intended to cover the following: - PICMG 3.0 IPM Controller - AMC.0 Carrier IPM Controller - AMC.0 Module Management Controller (MMC) - MTCA.0 MicroTCA Carrier Management Controller (MCMC) - MTCA.0 Enhanced Module Management Controller (EMMC) |